1. Field of the Invention
The present invention is directed to testing integrated circuit designs. More specifically, but without limitation thereto, the present invention is directed to high speed scan testing of an integrated circuit design.
2. Description of the Prior Art
Scan testing of flip-flops, or flops, and associated random logic in integrated circuit designs is typically performed at a clock speed that is limited by the maximum supply current that may be dissipated by the integrated circuit. Built-in self-test (BIST) uses scan chains with a low-frequency shift register and a scan input for tester precompression.